Intel's CEO explained the CPU shortage in December 2019. The 14nm to 10nm jump was planned at 2.7x transistors, and the yield bill is now due.
At the annual Credit Suisse technology conference in December 2019, Intel chief executive Bob Swan walked through the company's manufacturing problems and what it plans to do next. We went through his remarks and checked them against where the industry is, and they left us more confident than before that TSMC (2330), Taiwan listed, holds the lead in advanced process technology.
Key takeaways
- Swan gave three reasons for the CPU shortage: demand grew 21% against a plan of 10%, modem chips took capacity, and the high-end node slipped. The third one is the real one.
- Intel pushed too hard at each node. From 22nm to 14nm it raised transistor count 2.4x, and from 14nm to 10nm it planned 2.7x, against the 2x every 18 months of Moore's Law. Yields could not keep up.
- TSMC moves in small steps with an optimized version between every node: double patterning, exposing a layer twice to draw finer lines, at 10nm and then 7nm; then extreme ultraviolet lithography (EUV) replacing three to four mask layers, the patterned steps that print a chip, to make 7nm+; then EUV into 5nm. High yields fund the next node.
- 2022 is the checkpoint. AMD may ship 5nm as early as 2020 and Intel plans 7nm for 2022, while TSMC plans 3nm for 2022. If Intel misses again, the gap is two full generations and outsourcing to TSMC becomes a serious question.
Why Intel ran short of CPUs
Intel's CPU shortage has been holding back PC shipments, and the company took the unusual step of posting an apology on its own website. At the Credit Suisse conference Swan gave three reasons for the shortage.
- CPU demand came in stronger than planned. Intel had modeled 10% growth. Actual growth was 21%, far above plan.
- Mobile modem chips ate into capacity. Intel had high share in phone modems and wanted to build them in house. It has since sold that business to Apple.
- The high-end node slipped. Intel put the 10nm desktop processor on hold, so to raise performance on the existing 14nm line it had to add cores, which means bigger and bigger die.
The real driver is the third one. Yield problems have kept 10nm from shipping, and with no capacity available on the newer node, Intel has been left adding transistors at 14nm and growing die size to buy performance. That is a misallocation of capital. The engineering budget should be going into the next process. Otherwise, when a competitor ships parts on a new node with lower power and higher performance, Intel's answer is another round of bigger 14nm die.
Intel noted that Moore's Law historically meant transistor count doubling every 18 months. But going from 22nm to 14nm, transistor count on the processor rose 2.4x, and the plan from 14nm to 10nm was 2.7x. The bar was set too high, and problems kept surfacing. When each node upgrade is that large (more than a doubling of density), yields fall behind. Poor yields delay the node, delays stack up more capital spending, profit falls, and that squeezes the capital budget for the following node. You end up behind on both capacity and technology.
The harder a company pushes to skip a step, the more likely its yields fail. TSMC has done the opposite: a small step at every node, with an optimized half-step version in between, so every major node arrives de-risked and gets refined after it ships.
The 7nm sequence shows the approach clearly. TSMC first used double patterning for 10nm, then double patterning again for 7nm, then swapped EUV in for three to four mask layers to create 7nm+, and then brought EUV into 5nm. Each step optimizes one thing, ships a small revision each year, and only moves forward once that revision yields well enough.
Being ahead is what gives TSMC the room to optimize step by step, and that is precisely why it advances faster. High yields let it ramp to volume and book the revenue. Revenue growth covers the depreciation that comes with the capital spending. The profit and cash flow that generates go back into research and development on the next node, which extends the lead. That loop has put TSMC ahead on process, and today TSMC is the only company able to run EUV in volume production. That is why the major chip designers are all lining up for its 5nm and 7nm capacity to get their higher-end products out.
What Swan is really telling Intel to do
Swan's message at the conference was that Intel should stop chasing the 90% of the CPU market it already dominates and start aiming at 30% of the much larger semiconductor market. Two things follow from that framing.
- Falling behind on advanced process is letting AMD keep taking CPU share.
- It confirms how important heterogeneous integration, combining different kinds of chips in one package, and 3D packaging have become in high performance computing chips.
How far behind Intel actually is
Intel has not ignored the semiconductor market outside CPUs. It has just not done it well. Look at its moves over the past few years and you see acquisitions used to shore up the products it could not build: Altera in field programmable gate arrays (FPGAs) in 2015, Mobileye in automotive chips in 2017. But high performance computing is about combining products into one system, not running each of them on its own.
CPUs still matter, of course, and with a leading process behind it AMD has genuinely caught up. Once AMD moved to TSMC's leading node it began shipping parts that compete on performance, so Intel's share was always going to come under pressure. On top of that, what Intel shipped in 2019 was a low power 10nm chip. The real high performance PC and server parts are not due until 2020, a full year behind TSMC.
AMD's 5nm chips may arrive as soon as 2020, while Intel's roughly equivalent 7nm process is currently planned for 2022. Given the experience with 10nm yields, there is reason to worry that date slips too. TSMC, meanwhile, plans 3nm for 2022, which is roughly equivalent to Intel's 5nm. If Intel still cannot ship 7nm products by then, the two are formally two generations apart. At that point Intel's position gets much more painful, to the point where it would need to think seriously about handing production to TSMC.
Our view: 2022 is the moment that decides whether Intel is genuinely two generations behind.
Heterogeneous integration and 3D packaging matter in high performance computing
There are three technical routes to keep raising chip performance.
- Process scaling. With EUV in hand, getting to 3nm is not a problem, and 1nm to 2nm is still worth attempting, but below 1nm is close to impossible.
- 3D packaging. Stack in three dimensions to raise performance within a fixed footprint, and go a step further with heterogeneous integration by packaging several different kinds of components together.
- New materials. Higher frequency materials for more speed.
Heterogeneous integration means taking chips of different types and combining them with system level 3D packaging, which raises performance and cuts power. More than half of TSMC's customers on nodes beyond 7nm already use its wafer level 3D packaging. Read alongside what Intel said, that tells you semiconductors are no longer only about scaling. Heterogeneous integration matters too.
But heterogeneous integration takes real integration capability, and Intel's production record on products other than CPUs looks weak next to its CPU success. It bought technology in other product lines, yet Mobileye is jumping from 28nm to TSMC's 7nm in 2020. Altera's FPGA business, after Intel acquired it, never shipped a product on a leading node and lost large share to Xilinx. CPUs are the only product line where Intel's manufacturing is genuinely strong, and it has never shipped a successful GPU. Its position in cross chip heterogeneous integration packaging is nowhere near as strong as TSMC's, which serves every designer. TSMC already gets close to 10% of revenue from packaging and keeps shipping optimized versions of its 3D packaging. That makes the catch up harder still for Intel.
Bottom line: we stay positive on TSMC's process lead and on AMD taking more share
Swan's remarks at this conference laid out both the bind Intel is in on advanced process and the growing importance of heterogeneous integration and 3D packaging, and both make TSMC's competitive advantage look stronger. TSMC's customers will use that process lead to bring out better products and take share from their rivals. So we stay positive on the TSMC alliance, meaning TSMC and its fabless customers, built on that process lead. Given where TSMC sits, its valuation within semiconductors should, in our view, keep moving higher over the long run.